Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCan conditional builds be performed in VHDL?
I'm relatively new to VHDL and am looking for a way to perform conditional builds. I'm aware of the `ifdef that is available in Verilog, but am trying to find a comperable method in VHDL.
Altera_ForumHonored Contributor
Honored ContributorI just tried a test case using the generate statement and generic parameter. That
looks like it will do what I need. Thanks for the tip.
