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Altera_Forum
Honored Contributor
Honored ContributorCan conditional builds be performed in VHDL?
I'm relatively new to VHDL and am looking for a way to perform conditional builds. I'm aware of the `ifdef that is available in Verilog, but am trying to find a comperable method in VHDL.
Altera_ForumHonored Contributor
Honored ContributorDepending on what you are doing perhaps the "generate" statement can help.
