Can an external pull up on an open drain pin go to a voltage greater than VCCIO?

At final you can try to add a voltage divider with 3 resistors such as getting no more than 1.8V at the "upper end" of the lower resistor connected between FPGA CONF_DONE and ground but more than the required 2V the upper resistor connected between 3.3V and the µC. The third resistor being installed between these two connect FPGA and µC, also providing the voltage drop to bridge. Maybe tricky to scale this to ensure high and low levels are within the limits required by the FPGA and µC but both pins are high ohmic, thus this might be worth thinking about...