Can Altera FPGA support DDR2 or DDR3 interchangable memory of PC?

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Can I change the timing parameters for memory controller when it is running?

or could the controller get those timing parameters from memory automatically while initializing?

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In general the answer to both questions is yes. This is how motherboards work; they read the SPD EEPROM on the DDR DIMM and configure the memory accordingly.

Read the user guide for the DDR2/DDR3 controller, that should tell you if the parameters are programmable at run-time. You can also use Modelsim to simulate the DDR controller and DDR memory. Your testbench can then reprogram the controller for different DDR settings. The DDR models from Micron and others will report if you are accessing the memory with incorrect timing.

Cheers,

Dave