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Altera_Forum
Honored Contributor
Honored ContributorCamera Link - FPGA I/O protection
For a new desing I am planning to implement the Deserializer for CamerLink in the FPGA to replace the Deserializer chip. To protect the FPGA I/O's (ESD) I thought to place a "sacrificial" LVDS buffer...
Altera_ForumHonored Contributor
Honored ContributorRegardless wether you use ESD protection or not:
I would never ever interface the Higher-Level-System directly from the FPGA. You'll never know what you've to handle with. Just my 2 cents...
