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Altera_Forum
Honored Contributor
Honored ContributorCamera Link - FPGA I/O protection
For a new desing I am planning to implement the Deserializer for CamerLink in the FPGA to replace the Deserializer chip. To protect the FPGA I/O's (ESD) I thought to place a "sacrificial" LVDS buffer...
Altera_ForumHonored Contributor
Honored ContributorIMHO, a sacrificial buffer is the wrong way to go. Yes, you protect the FPGA but then you'll be replacing your buffer often too..
If ESD is important, you should implement proper ESD protection instead. As jvov suggested, there are ESD protection devices for popular protocols which may fit your needs. If that doesn't work out, you can just add in your own ESD protection circuitry, using discrete diodes.
