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Altera_Forum
Honored Contributor
Honored Contributorbypass the need for dedicated clock pins
Hi, i am doing a project at the university and the card that my fpga would be on is already printed (The FPGA is EP2S130). I need to get data from SERDES on another card (in LVDS), and becaus...
Altera_ForumHonored Contributor
Honored ContributorThe other problem is, that PLL clock processing isn't available for clock from I/O pins. This means, that you need to supply the LVDS fast clock (1/2 data rate) from the transmitter side. Frame synchronization must use an additional signal or sync pattern embedded in the data stream.
