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Altera_Forum's avatar
Altera_Forum
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14 years ago

bypass the need for dedicated clock pins

Hi, i am doing a project at the university and the card that my fpga would be on is already printed (The FPGA is EP2S130). I need to get data from SERDES on another card (in LVDS), and becaus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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I didnt quite understand, is there a way to tell QUARTUS to ignore this problem if i can assure that the data rate would be slow or medium speed?

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The problem is, that the Stratix II devices (as far as I'm aware of), don't have a clock path available to feed the clock input of a dedicated SERDES blocks from a regular IO pin. So you can't use the SERDES hardware.