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Altera_Forum
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14 years ago

Bug in Quartus II (BDFs + Verilog Parameters)

In Quartus II (11 at the moment, not tried other versions), when updating parameters from within the verilog file and re-creating the symbol file, then updating symbol file in the BDF, the parameters...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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the parameters in the BDF do not change

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Which parameters to you mean? The module's defpars or the actual values of the instantiation? It's many years, that I've been using schematic entry for designs, but I guess you would want the instance parameter to be kept, as in a HDL module respectively component instantiation?