Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorBug in Quartus II (BDFs + Verilog Parameters)
In Quartus II (11 at the moment, not tried other versions), when updating parameters from within the verilog file and re-creating the symbol file, then updating symbol file in the BDF, the parameters...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- the parameters in the BDF do not change --- Quote End --- Which parameters to you mean? The module's defpars or the actual values of the instantiation? It's many years, that I've been using schematic entry for designs, but I guess you would want the instance parameter to be kept, as in a HDL module respectively component instantiation?
