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Talavai's avatar
Talavai
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2 years ago

Bug in HDMI TX IP preventing back-to-back writes to HDMI I2C master

HDMI IP 23.2-19.7.2, being configured as Source/TX with FRL support, AXI4S video interface (VVP Full), and I2C master, does not accept back-to-back writes to I2C master registers. The attached simulation waveform demonstrates that only one write strobe (Avalon MM write pulse) was passed through the DEMUX to the I2C master, while the external Avalon MM master performed three writes (to SCL_LOW, SCL_HIGH, and SDA_HOLD). Registers read back sequence confirms that only the first register in the write sequence, SCL_LOW, is modified.

 

Fpga Devkit

2 Replies

  • Talavai's avatar
    Talavai
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    2 years ago

    Please disregard this question as posted in the incorrect forum.

  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Talavai,

    Thank you for reaching out.

    As you mention this question is posted in the incorrect forum and duplication question to this case (Bug in HDMI TX IP preventing back-to-back writes to HDMI I2C master) .

    With that, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

    Thank you.

    Best Regards,

    ZulsyafiqH_Intel