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Altera_Forum
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8 years ago

Buffer chain output from DLL in ALTDLL

Hi, I require clocks with different phase shifts. Theoretically, the outputs at each stage of the buffers in the buffer chain of DLL in ALTDLL megafunction should do it. However, ALTDLL outputs only ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hi, the main reason behind sampling with clocks with different phases was the sampling rate limit of the ADC. From what I understand, for using altlvds, I need to sample it at 1500Mbps which won't be possible. The best option I had was to have a locked DLL and get the clocks out from the cascaded buffers, but it turns out that I can't do it.

To increase the duration between the phase-delayed clocks, I can reduce the clock frequency to a minimum of 150MHz and have 8-12 phase-delayed clocks. Thus, I can increase the time gap to 800ps. The processing after I receive the sampled signal is relatively simple; thus, I am not constrained by the speed of input to the DE4 board. Can I implement it with the PLL scheme you had suggested? Please let me know if you find any better options.

Thanks. :)