Buffer chain output from DLL in ALTDLL

Sorry, 250ps, not 25ps. Still, that granularity is really fast, and I don't think you will achieve it with generic structures. Let's pretend you were capturing the data with a single clock(which in many ways is much better since it would have minimal variation in delays), and it would require a 4GHz clock to get the same number of samples. Instead you're trying to build this with generic FPGA structures which have a lot more variation.

Your on-die variation on the clock trees will probably be large enough to swamp out 250ps. Add that things will not be perfectly laid out(the clock trees are not identical down to the last ps, the data paths will be different to the different labs, etc.).

The reason I suggest altlvds is that it uses all dedicated silicon and therefore has much tighter controls. Basically do a altlvds_rx with /8 deserialization, and you'll basically get 8 bits of data. But that won't run at the speeds you want either. At best you might be able to do 1500Mbps sampling (so 3 samples for every 2ns data bit instead of 8 samples). That may not be enough for what you want though.