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Altera_Forum
Honored Contributor
8 years agoThere are many things here that I don't understand.
Yes, the I/O standard is LVDS. The function I'm trying to implement is for sampling. For sampling, I am using the Terasic data conversion board, which gets sampling clock from the DE4 board using LVDS clock pins from HSMC-A connector. At each microsecond, I have to use one out of eight phase-delayed clocks (which are selected using a MUX) for sampling. That's why eight phase-delayed clocks need to be synchronized. Can you please suggest any method to implement this scheme. I am not sure if the altlvds megafunction will work, as it serializes the data and sends at very high frequency while I need to select a phase-delayed 500MHz clock at each microsecond.