Forum Discussion
Honored ContributorBooting of Cyclone
I have some questions about booting a Cyclone FPGA (EP1C3 or EP1C6).
I'm making a design that has an ARM7 microcontroller and a Cyclone FPGA. I'd like to store the program for the FPGA inside the microcontroller flash (or otherwise make it possible to update the FPGA program via the microcontroller) What's the best way to do this? Also, on a related note, what sort of boot times can I expect as my designs grow larger? What's the rate at which the FPGA can read and process the program data?12 Replies
Altera_ForumAfter I've read more about the Cyclone III I went and ordered the Cyclone III starter kit and this mezzo to pin header adapter: http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=39&no=218
Looking forward to working with this platform, it promises some great performance.- Altera_Forum
I have found very simple to build an adapter board from the mezzo conector to simpler GPIOs connection points. :)
- Altera_Forum
Well, I need a board with some GPIO available not on a mezzo connector.
- Altera_Forum
The latest Cyclone III devboard costs less than 300USD so I recommend you to purchase it, you can try all the "cool" facilities that anakha explained at a very low cost. ;)
- Altera_Forum
Ok, then I will need a new devel board. This is what I have for the Cyclone: http://www.dallaslogic.com/ezfpga_cyclone_c3c6.htm
- Altera_Forum
No, they are not compatible in any way.
- Altera_Forum
I gotta check the datasheets on that but are the Cyclone3 QFP144 devices pin compatible with the Cyclone devices in that package? (As in, are the non-configurable pins in the same locations?)
- Altera_Forum
Hi baldur,
If possible, I really, really **strongly** suggest you to use a Cyclone 3 device (EP3C5 or EP3C10 for example). There is a passive parallel configuration scheme which does not exists in Cyclone devices. FPGA configuration data are supplied on a byte wide scheme , and can clocked at least up to 100 MHz... Very simple to implement, yet very efficient. For example, uncompressed bitstream for an EP3C10 is about 3.3 Mbits (~412 Kbytes). Let's say your ARM7 clock data bytes at 10 MHz (optimistic ?) , you can expect a configuration time of about 41 ms. The bad news is that in passive // mode, bitstream can not be compressed. But the good news is that configuration time is constant, so this is a guaranteed time. I use passive // configuration scheme on a custom board with a EP3C10, but since I have no microcontroller on the board (I use a NIOS inside the FPGA) , I use a CPLD (from Xilinx :D ) which converts data bits from a SPI serial flash to 8 bits data, at an equivalent bit rate of 96 Mbits/s (12 Mbytes/s). I got configuration time of about 35 ms. Works very well. Cyclone 3 are pure pleasure ... really low cost and low power and cool configuration modes. Hope this help. - Altera_Forum
Thank you for your help. How do I wire it up for this passive serial mode?
- Altera_Forum
The boot time partly depends on the design size - if compressed bitstreams are used, which is generally advisable. The nominal configuration bitstream size defines the upper bound for boot time then.
