I have some questions about booting a Cyclone FPGA (EP1C3 or EP1C6). I'm making a design that has an ARM7 microcontroller and a Cyclone FPGA. I'd like to store the program for the FPGA inside the microcontroller flash (or otherwise make it possible to update the FPGA program via the microcontroller) What's the best way to do this? Also, on a related note, what sort of boot times can I expect as my designs grow larger? What's the rate at which the FPGA can read and process the program data?

usually the best way to do this is in "Passive Serial mode" One of the Quartus outputs available is a .RBF (Raw binary File) And the Passive Serial mode looks like an SPI device. You may have to do an Endian Swap on the RBF, but you basically shift the data out, make sure you get the config done and go. We do this we several designs with various Cyclone and Stratix families. One thing if this is a new board, and you have a choice, I suggest moving to the newer Cyclone III family, It will give you a faster design, lower power, and at a lower unit cost. The maximum bit rate is 20 Mbps on Cyclone (If I remember correctly) and 20 or 40 Mbps So you can figure it as the worse case number of bits for the device. Usually it's pretty fast, unless you have a really slow SPI. Pete

The boot time is NOT a function of the internal design size of the FPGA. It is a function of the load time of the FPGA, which is always the number of configuration bits of the FPGA.

The boot time partly depends on the design size - if compressed bitstreams are used, which is generally advisable. The nominal configuration bitstream size defines the upper bound for boot time then.

Thank you for your help. How do I wire it up for this passive serial mode?

Hi baldur, If possible, I really, really **strongly** suggest you to use a Cyclone 3 device (EP3C5 or EP3C10 for example). There is a passive parallel configuration scheme which does not exists in Cyclone devices. FPGA configuration data are supplied on a byte wide scheme , and can clocked at least up to 100 MHz... Very simple to implement, yet very efficient. For example, uncompressed bitstream for an EP3C10 is about 3.3 Mbits (~412 Kbytes). Let's say your ARM7 clock data bytes at 10 MHz (optimistic ?) , you can expect a configuration time of about 41 ms. The bad news is that in passive // mode, bitstream can not be compressed. But the good news is that configuration time is constant, so this is a guaranteed time. I use passive // configuration scheme on a custom board with a EP3C10, but since I have no microcontroller on the board (I use a NIOS inside the FPGA) , I use a CPLD (from Xilinx :D ) which converts data bits from a SPI serial flash to 8 bits data, at an equivalent bit rate of 96 Mbits/s (12 Mbytes/s). I got configuration time of about 35 ms. Works very well. Cyclone 3 are pure pleasure ... really low cost and low power and cool configuration modes. Hope this help.

Booting of Cyclone | Altera Community

12 Replies

Altera_Forum
Honored Contributor
18 years ago
The boot time is NOT a function of the internal design size of the FPGA.

It is a function of the load time of the FPGA, which is always the number of configuration bits of the FPGA.
Altera_Forum
Honored Contributor
18 years ago
usually the best way to do this is in "Passive Serial mode"

One of the Quartus outputs available is a .RBF (Raw binary File) And the Passive Serial mode looks like an SPI device.

You may have to do an Endian Swap on the RBF, but you basically shift the data out, make sure you get the config done and go.

We do this we several designs with various Cyclone and Stratix families.

One thing if this is a new board, and you have a choice, I suggest moving to the newer Cyclone III family, It will give you a faster design, lower power, and at a lower unit cost.

The maximum bit rate is 20 Mbps on Cyclone (If I remember correctly) and 20 or 40 Mbps

So you can figure it as the worse case number of bits for the device. Usually it's pretty fast, unless you have a really slow SPI.

Pete

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Booting of Cyclone

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