Block Design Files and AHDL

I like schematic from a documentation perspective, as things tend to make more sense when you can see them. But that depends what it is, as case statements are much clearer in an HDL. I see many designs where the top-level/s that connect blocks are schematic and everything below is HDL. (In these cases, you can write out an HDL description of the .bdf from Quartus if you need it for simulation.)

HDLs tend to be used for a variety of reasons. They are tool independent(a Verilog shoudl be synthesizable by any tool, technically). They have some nice features that allow parameterization and what not become much easier. Lots of things are easier to change in HDL(although I would argue some things are easier to change in a schematic, like bringing a signal across hierarchies.) Probably the biggest thing you'll hear is vendor independence for VHDL and Verilog. VHDL, to my understanding, was started by the government(break out your tin-foil hat) as an independent way to describe schematics that were being done, but they eventually became synthesizable. But that being said, having converted many VHDL/Verilog designs across vendors, the process can be far from seamless.