Binary Count - elf download failure

I am attempting to run the NIOS II program example 'binary count' but seem unable to download the elf file. The specific error is: "Downloading ELF Process failed." From the error window there is no more information other than that.

I am running on the Altera DE2 board, Cyclone II EP2C35F672C6N. My initial attempt to run it failed due to not enough memory on my SOPC. I added SDRAM running on a clock that is 3 ns slower than the clock used for the NIOS II processor. Which was done through a pll.

Looking up this error I found that the most common root of this problem is a timing issue. I am not sure what the timing should be for this project. I chose 3 ns as the clock for SDRAM because that is what the tutorial I followed chose.

If I limit the memory for the program by choosing code optimization and using small C library, and using onboard memory than I can get the LED and the HEX to light up. But when I introduce SDRAM memory than I run into the ELF file error. If I try to create a new BSP I run into the same issue.

SOPC Content:

-CPU - NIOS II

-SDRAM

-JTAG Interface

-System ID

-LCD Display

-Button PIO - 4 bit input (toggle switches)

-LED PIO - 8 bit output

-Seven Seg PIO - 16 bit output

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY memTest IS
    PORT(KEY:                                                         IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          CLOCK_50:                                                 IN STD_LOGIC;
          LEDG:                                                         OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          SWITCHES:                                                    IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          HEX:                                                        OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
          -- 16 X 2 LCD Module
          LCD_ON,                                             -- Power ON/OFF
          LCD_BLON,                                           -- Back Light ON/OFF
          LCD_RW,                                             -- Read/Write Select, 0 = Write, 1 = Read
          LCD_EN,                                                -- Enable
          LCD_RS :                                                     OUT STD_LOGIC;     -- Command/Data Select, 0 = Command, 1 = Data
          LCD_DATA :                                                 INOUT STD_LOGIC_VECTOR(7 downto 0); -- Data bus 8 bits
         
          -- SDRAM
          DRAM_CLK, DRAM_CKE :                                     OUT STD_LOGIC;
          DRAM_ADDR :                                                 OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
          DRAM_BA_0, DRAM_BA_1 :                                 BUFFER STD_LOGIC;
          DRAM_CS_N, DRAM_CAS_N, DRAM_RAS_N, DRAM_WE_N : OUT STD_LOGIC;
          DRAM_DQ :                                                 INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
          DRAM_UDQM, DRAM_LDQM :                                 BUFFER STD_LOGIC 
          );
END memTest;
ARCHITECTURE Structure OF memTest IS 
    COMPONENT niosII
        PORT (
              -- 1) global signals:
                 signal clk_0 : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
              -- the_button_pio
                 signal in_port_to_the_button_pio : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
              -- the_lcd_display
                 signal LCD_E_from_the_lcd_display : OUT STD_LOGIC;
                 signal LCD_RS_from_the_lcd_display : OUT STD_LOGIC;
                 signal LCD_RW_from_the_lcd_display : OUT STD_LOGIC;
                 signal LCD_data_to_and_from_the_lcd_display : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
              -- the_led_pio
                 signal out_port_from_the_led_pio : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
              -- the_sdram_0
                 signal zs_addr_from_the_sdram_0 : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
                 signal zs_ba_from_the_sdram_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal zs_cas_n_from_the_sdram_0 : OUT STD_LOGIC;
                 signal zs_cke_from_the_sdram_0 : OUT STD_LOGIC;
                 signal zs_cs_n_from_the_sdram_0 : OUT STD_LOGIC;
                 signal zs_dq_to_and_from_the_sdram_0 : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal zs_dqm_from_the_sdram_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal zs_ras_n_from_the_sdram_0 : OUT STD_LOGIC;
                 signal zs_we_n_from_the_sdram_0 : OUT STD_LOGIC;
              -- the_seven_seg_pio
                 signal out_port_from_the_seven_seg_pio : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
              );
    END COMPONENT;
    
    COMPONENT sdram_pll
        PORT(inclk0: IN STD_LOGIC;
            c0: OUT STD_LOGIC;
            c1: OUT STD_LOGIC);
    END COMPONENT;
SIGNAL DQM : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL BA : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL pll_cl: STD_LOGIC;
BEGIN
nios_system: niosII PORT MAP (pll_cl, KEY(0), SWITCHES, LCD_EN, LCD_RS, LCD_RW, LCD_DATA,
LEDG, DRAM_ADDR, BA, DRAM_CAS_N, DRAM_CKE, DRAM_CS_N, DRAM_DQ, DQM, DRAM_RAS_N, DRAM_WE_N,
HEX);
neg_3ns: sdram_pll PORT MAP(CLOCK_50, DRAM_CLK, pll_cl);
    
END Structure;

Edit: Reset is set to KEY[0] which is a HIGH until pressed.