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You have been talking of transferring signals (integer numbers) between modules. This normally means, that the signal exist as an output in the interface of one module and as input at one or several other modules. In this case a signal of type wire would be used in the top module to connect the underlying modules.
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Yes, that is exactly what I mean :)
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The technique is described in any Verilog textbook or tutorial and can be learned from design examples, I think. Verilog, unlike VHDL, doesn't allow array signals in module interfaces, so each number respectively bitvector has to be defined separately. Or the two-dimensional bitvector has to be mapped to a large one-dimensional one. This restriction is one reason, why I prefer VHDL for hierarchical designs.
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Actually, I am using SystemVerilog and it can remove this restriction.
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Physically, a signal has to be routed through the FPGA for each bit, so 576*32 bit is implying a considerable routing effort. There may be alternatives in design structure, depending on the purpose of the said signals. A key question is, if the
numbers have to be accessed in parallel or may be transferred sequentially, at least in part. If the signals allow sequential access, they can be possibly stored in embedded RAM also.
But this can't be decided without knowing the design purpose and functional details.
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It does allow sequential access.
I understand what you mean now. I need to implement an common memory module ( like RAM) to store 576 integer numbers instead of transferring them.
Thank you for your help, I will try this.
BTW, Is it right to use megafunction plugin to create embedded RAM ?
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