Altera_Forum
Honored Contributor
Honored ContributorAverage in VHDL..?
Hi everyone, can anyone please give me an idea about how to average the given data (for exampale say decimal 1 to 10). thank you.
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Altera_ForumHonored Contributor
Honored Contributora <= b/c; is perfectly synthesisable. But, as with verilog, there will be 0 pipelining so the performance will be poor. So you still need to use the megafunction.
Like carl said, its best to divide by 2^n, as this is just a bitshift and essentially free in terms of logic.
