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Altera_Forum's avatar
Altera_Forum
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18 years ago

Avalon Slave Port

Hello to all, I have a Stratix II dev Kit and I made a design with a Nios II, an onchip memory, a tristate bridge and a custom "Typical Avalon MM-Slave" added with the template on SOPC Builder 7.2...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello sealab,

1) I'm Not sure to understand why you want to use chip_select and write_n signals. Your custom peripheral should not handle these signals if you only need to drive Leds. Remove it from "component editor" if you don't need it (I assume these signals have been added by the template you've chosen).

2) Did you create your component with your own HDL file(s) or w/o any file (just interface signals)? Because there is a bug on the 7.2 where interface signals are not exported to the top level entity! (Topic on this bug: http://www.niosforum.com/pages/forum.php?cat_id=5)

Anyway, if you send me a picture of your SOPC system and your graphical design top level design with your inputs/ouputs signals (under quartusII) maybe I could give you more help.

Regards.

-Pierre