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Altera_Forum's avatar
Altera_Forum
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14 years ago

Avalon on a backplane ??

Hello, In my current project, I'm thinking about using an architecture with one FPGA Card which hosts the Nios 2 processor and some CPLD cards which host some specific VHLD slave funcions. M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You can tun the external bus at a lower frequency, just stick a clock crossing bridge in your SOPC.

On the external bus, you can also use the same lines for read-data and write-data.

For some reason, the Avalon specificatio no longer documents MM tristate masters and slaves.

But the options are still available in SOPC.

You can also ditch Avalon for the external bus completely. Just write your own bridge.