Avalon MM Interface readdata signal [511:0]

The Avalon spec doesn't specify when a burst request is generated. It is only concerned with how it is implemented. In most cases you can expect burst requests when A) A CPU is filling up a cache line, B When a DMA controller is being used, C) If you are implementing a bus like PCIe or RapidIO. For A) to happen, the CPU must have cache, like the ARM in an SoC chip or higher end NIOS soft processors. The free NIOS doesn't have a cache. For B, the software, either a device driver or bare metal, must set up a DMA request. In that case, the burst will depend on how the DMA request is made. In case C), the other end may or may not request a burst transfer.