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Altera_Forum's avatar
Altera_Forum
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13 years ago

Avalon data bus between two fpgas

Hi, I need a little advice/direction regarding connecting two fpgas via a bus. HW setup Stratix III (DE3) Stratix V 8 x LVDS Tx pairs ------------------...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Yes. I will need a frame clock as well. I think I missed it out and its available in the hardware layout as well. Will double check.

Also, I checked the Avalon ST spec. It has a valid signal. This should be usable to generate the frame clock using the Alt-lvds megafunction itself.

Thank-you. Seems there are no obvious mistakes.. I guess I'll go ahead and play.

Cheers

Zubair