Avalon data bus between two fpgas

Try it and see.

Since the ALTLVDS interface will be serializing and deserializing data, you will also need a frame clock. If your data can accommodate some 'extra' symbols, then you can convert the Avalon-ST start-of-packet, end-of-packet, etc, wires into symbols in the data stream. This is how the JTAG-to-Avalon-ST interface works - read the following for details

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.zip

This might give you a few ideas.

Cheers,

Dave