Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorautomatic slave module generation
I have written a lot of slave IP lately, and have developed somewhat of a template/style that I use. Sort of like Altera's template, but much cleaner, in my opinion. While having well-establis...
Altera_ForumHonored Contributor
Honored Contributorthat sounds like a cool project
i'm not stuck with this particular tedious task, but i have been thinking of writing applications for others. for example, Quartus can't generate an example instantiation with System Verilog multi-dimensional ports which leaves me with wasting time doing it manually my idea was to create a web-based application where you paste in the module declaration and get an instantiation, including multi-dimensional ports. it could also be more flexible than Quartus, for example you could customize the signal name (append _sig, _v, nothing) anyhow, my 2 cents is to make it a web application. i'd be interested in collaborating to build a suite of tools to cut out tedious work
