Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Asynchronous Signal

Hi. I have a problem that my FPGA design failing after several seconds. The code purposes isto measurement frequency from external signal generator (50kHz)*. I'm working with 50Mhz clock, LPM_Divi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You should also check that your synthesizer has recognized your state machine properly (use the rx viewer/state machine viewer). Sometimes if it can't recognize a state machine due to coding issues, you can get some unexpected results.