Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Asynchronous Signal

Hi. I have a problem that my FPGA design failing after several seconds. The code purposes isto measurement frequency from external signal generator (50kHz)*. I'm working with 50Mhz clock, LPM_Divi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

This thread seems to offer some information for you to look at. The problem is with asynchronous signals you have metastability. When you register the external signal you help improve this which eliminates your problems. I believe there is a document link in the thread which discusses it in further detail.

http://www.alteraforum.com/forum/showthread.php?t=39099