ASMI clk_in frequencies

Hi,

I am using ASMI_PARALLEL core in a Cyclone III device. I am using ECPS16 device.

Boot area: 0x000000 - 0x080000

Temp area: 0x080000 - 0x0F0000

What I do in my FSM is first store the upload firmware image to the temp area and when it has completely been received I verify the checksum and copy it to the boot area.

Writing to the boot area is for me the critical window and my interest is to minimize it. For this I have tried several clk_in frequencies for the alt_asmi core, but somehow the results don't look consistent.

The critical window means:

1. erase 8 sectors of the boot area

2. read blocks from temp area one by one and write them to the boot area (256 bytes at once)

These are the results I got with various clock frequencies for the ASMI:

10.0 MHz => 16 sec

12.5 MHz => 14 sec

15.0 MHz => 14 sec

16.6 MHz => 12 sec

18.7 MHz => 24 sec

20.0 MHz => 34 sec

25.0 MHz => 34 sec

The userguide of the asmi core says 25 MHz is the maximum frequency (supported only in fast read mode).

Could anyone give me a hint why these numbers look like this? I was expecting some linear decrease of erase/copy time in relation with the input clock.

Thanks!