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Honored Contributor
Honored ContributorArria10 HPS Fpga to Sdram cannot be configured above 64 bits
Hi All, I want to use the fpga to sdram path in Arria 10 HPS. I want to connect a 256bit AXI interface operating at 125 Mhz from a third party IP to this port. I had a couple of questions: ...
Altera_ForumHonored Contributor
Honored Contributorganeshmirajkar -
You're talking about the three FPGA to HPS SDRAM interfaces, correct? If you select Port Configuration 3 in the HPS parameter editor then the F2SDRAM 0 and F2SDRAM 2 interfaces are both 128 bits wide, and F2SDRAM 1 is disabled. If you select Port Configuration 4 then F2SDRAM 0 is 128 bits, F2SDRAM 1 is 32 bits, and F2SDRAM 2 is 64 bits. So you're correct that you can't get 256 wide on one port, but you can get 128 wide. And if using two ports will work for your application then you can get 256 wide by using F2SDRAM 0 and F2SDRAM 2 in Port Configuration 3. By the way, the ES1 marking should be on the device package if you can see it. Bob
