Arria10 HPS Fpga to Sdram cannot be configured above 64 bits

Thanks Derim for the reply.

You are right. The FPGA-to-HPS SDRAM interface supports six command ports each 64 bit, allowing up to six Avalon-MM interfaces or three AXI interfaces. Each command port can be used to implement either a read or write command port for AXI, or be used as part of an Avalon-MM interface. The AXI and Avalon-MM interfaces can be configured to support 32-, 64-, 128-, and 256-bit data. Since there are 4 data ports each 64bit. Look at the attached picture. What happens is, you cannot configure the FPGA2SDRAm port in HPS for a width above 64bit. This applies to following Arria10 device. 10as066n3f40I2sges. I am not sure if the tool will allow me to configure a higher data width if I use another FPGA. I am using the arria10 soc development kit and it has this device.

I checked with Altera and they said that this device has some problem(probably some ECO is done) and that why this width is limited to 64 bits only. but theoretically, it can go upto 256bit.

Now, 64 bit is ok, but I need a bandwidth of 32gbps on this port and to get that i will have to clock it at 500Mhz. That would be impossible for the logic which does conversion from 256bit@125Mhz to 64bit@500Mhz. Anyways, now Instead of using this port, I am using the FPGA2HPS port to access sdram through L3 interconnect. L3 interconnect works at half of cpu speed and has a 64bit interface to sdram scheduler in sdram l3 interconnect. The good thing is fpga-to-hps port can be configured as 128 bits. So my conversion logic needs to run only at 250 Mhz, which I think I will be able to manage.

Let me know what you think.