Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorArria V LVDS IO
Hello, Knowledge base (http://www.altera.com/support/kdb/solutions/fb128391.html) states: "You must assign the LVDS I/O standard-enabled pins in the right I/O bank as PLL clock input pins only"...
Altera_ForumHonored Contributor
Honored ContributorI can't wait. It will probably be after the 4th... never waste a holiday to delay a release. :-)
I think I figured out what knowledge db entry means. I think it means that you can only select the LVDS I/O standard if you intend to use the selected pins for a PLL input. Let's see what sp1 will do.
