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Altera_Forum
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13 years ago

Arria V LVDS IO

Hello, Knowledge base (http://www.altera.com/support/kdb/solutions/fb128391.html) states: "You must assign the LVDS I/O standard-enabled pins in the right I/O bank as PLL clock input pins only"...
Altera_Forum's avatar
Altera_Forum
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13 years ago

You are correct. 12.1 sp1 lets me assign LVDS to the clock input pins on the right side (8 pins total). However, 12.1 sp1 has an incorrect pin layout for the device I am using - that was fixed in 13.0 -- So, my choice is to trust incorrect version number 1 or incorrect version number 2.

I guess I will file support request and see what they mean. The SR mentions the issue was found in 13.0sp1, which I cannot find.