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Altera_Forum
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8 years ago

Arria V GX - Clock problem

Hello! I just started with the Altera FPGAs and Quartus II, I am learning but I haven´t could do work my first sequential example. I have tried a combinational design (a switch with a led) and ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

Refer the thread which address the issue in detail.

https://alteraforum.com/forum/showthread.php?t=5112

Give slew rate in pin planner to eliminate the warning.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)