Arria 10 SX - The Fitter cannot place logic IO_LANE ???

I use the same Achilles board as joco83. I got the same error when trying to port my design to the board. It may be as sstrell writes that there is an I/O conflict with the HPS I have not looked at the HPS yet. But I noticed that the DDR4 test design from Reflex CES compiles. So I compared assignment from the two project and found some differences. These are the assignments I changes. I do not know which ones are responsible but afterwards the error is gone and the project compiles. Maybe the HPS_EARLY_IO_RELEASE OFF?

 -set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name OPTIMIZATION_MODE BALANCED +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING AUTOMATIC +set_global_assignment -name PROJECT_IP_REGENERATION_POLICY NEVER_REGENERATE_IP +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF  +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON  +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON  +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP OFF  +set_global_assignment -name HPS_EARLY_IO_RELEASE OFF  +set_global_assignment -name CVP_MODE OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF