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Altera_Forum
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15 years ago

Architecture timing issue

Hi, In my architecture I need to do the following divider: 100000000/ (conv_integer (Byte_1 & Byte_2& Byte_3)) when stat_cycle='0'. (24 bits) I'm working with 10Mhz clock. How do I k...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

i'm fairly certain one level of register retiming will work with a divider. multiple stages won't work (with anything)