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Altera_Forum
Honored Contributor
15 years agoArchitecture timing issue
Hi, In my architecture I need to do the following divider: 100000000/ (conv_integer (Byte_1 & Byte_2& Byte_3)) when stat_cycle='0'. (24 bits) I'm working with 10Mhz clock. How do I k...
Altera_Forum
Honored Contributor
15 years agoBasically no. Dividers need several pipeline stages, which cannot be done with a simple "/" operator. You have to use a divider IP block.
Why do you need such a large divide (24 bits)?