Analyzing Simulation result

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i don't have Modelsim installed on my system

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Altera has a free version; Modelsim Altera Edition. Download it and install it.

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but Quartus does produces a logic output... i'm also aware it's output could be viewed as text. That's what am interested in.

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Viewing generated code is a waste of your time.

Write VHDL or Verilog, then write a testbench, and confirm the tests pass in Modelsim.

Synthesize the design, along with timing and pin constraints, and generate an output netlist.

If timing passes, then run a simulation with the post-place-and-route netlist. Once you have confidence in your design skills, you can generally believe that a design that passes timing can be tested directly in hardware (since post-P&R simulation can take a while).

Bottom line is you do not need to read anything Quartus generates. Let *Modelsim* do that for you, and let a computer (via your testbench) test the code too.

Cheers,

Dave