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Altera_Forum
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9 years ago

altremote_update in Cyclon III

Hi all,

I am trying to implement the altremote_update megafunction in a cyclon III FPGA without success.

I followed the relative User Guide driving the altremote_update with a Finite State Machine and generating two configurations, one Factory and one Application (the configuration mode setting is to Remote).

These two configurations are combined together in a .jic files where I specified the start address 0x0 for the Factory and 0x100000 for the Application (exactly in the middle of my EPCS16).

In order to fit the two configurations in the EPCS16 device, I enabled the .sof file compression feature and after that I generated and downloaded successfully into the FPGA the file.

When the Factory configuration is running, I set the parameters enabling the Watchdog, the Cd_early, the OSC_int and the Boot Addr taking care for this last to write 22 bits instead of 24(so 0x040000 instead of 0x100000).

Before triggering the reconfiguration I checked the parameters in the input register performing a read action with read_source signal set to 0x3 and the values that I receive back are in line with the expected ones.

Now the problem: after the reconfiguration trigger, the configuration loaded is always the Factory and not the Application.

In order to find out the reason of that I read the status register with read_source signal set to 0x1 and the reconfiguration trigger condition field reports a CRC error as root cause of the Application configuration fail.

The boot Address is the expected one, as well as the Watchdog enable, the Watchdog Timeout and the Osc_int but Cd_early setting is wrong (it is set to zero while my expected value is one).

Just for testing purpose, I tried to set the boot address for the application configuration to 0x0 (the same boot address used for the factory) and in this case I had no CRC error after the reconfiguration trigger, but after a while I got the Watchdog timeout error. This is expected because in the Factory configuration there isn't a watchdog timer reset strategy implemented (as in the Application configuration).

My feeling is that I set a wrong boot address for the application configuration.

Could you please help me?

Thank you in advance.

Davide.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi all,

    I just received from Altera Technical Support the solution of my problem and I want to share it (maybe it can be useful for someone else) :

    # #############################

    From this SR database stated that you are using Quartus II v13.1.4. Is this correct? I checked from the remote update user guide, under Cyclone IV device, it mentioned that for the Quartus II software version 13.1 and onwards:

    • Width of 29 or 32 when reading the boot address.

    • Width of 24 or 32 when writing the boot address.

    • For active serial devices using the 24-bit addressing, such as EPCS128 or EPCQ128, boot_address[23..2] corresponds to the upper 22 bits of the 24-bits boot address. boot_address[1..0] is read as 2'b0.

    This should be applicable for Cyclone III too since the parameters for Cyclone IV and Cyclone III are the same. Thus when writing the application image boot address you need to set data_in[23..0]= 0x100000h and not 0x040000h.Write the 24bits and not the upper 22bits. Please try to do this and test the reconfiguration to the application image.

    # #################################################################