altpll component query

If you want to know the maximum system clock frequency your device can work normally. it mainly depends on the device (include fpga and sdram) and the temperature.

You can use eda gate level simulation to see whether your design can work well on your input clock, which provided several models.

If you want to know the highest frequency pll can export, I don't know either, but I think it must be higher than your device's maximum input clock.