Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Altmemphy with Cyclone IV E

Hi,

I am a university student at McGill working on a project involving the DE0-Nano board. For the project I need to get memory access and I was trying to figure out how to go about it. My professor mentioned he has used Altmemphy in the past with a Cyclone II, so I've been trying to figure out if that will work with the Cyclone IV E (which is what I believe to be on the board). I was reading through the handbook and noticed that the controller might have problems with the timing once it has been implemented. This might be a problem as the final result of the project could be used commercially. Has anyone successfully used Altmemphy with the DE0-Nano before or would I be better off trying to write my own memory controller (which would could make sure that there are no timing problems, although from what I hear it could prove to be quite a task)? Any help would be greatly appreciated.

- David

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    ALTMEMPHY is an old, frequently updated (if bugs found) and finished controller. You won't do any better than this core, especially if You're a beginner. Use Timequest analysis for timing requirement tests. If it is proved to work earlier - it WILL work later, because the core is still maintained by Altera.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Actually, the DE0-Nano board carries (ordinary) SDRAM not DDR2, so you won't need to (rather can't) use the ALTMEM_PHY.

    I browsed through the DE0_Nano's user manual: it is quite comprehensive and it should be easy enough to instantiate the SDRAM-function in your project.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for the help. I neglected to mention that we're (I'm working with a partner) not going to be able to use Nios II as our professor would prefer to avoid it and wants everything done in VHDL. Do you remember what part of the manual the information is in (I was probably reading too quickly and missed something)?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Starting from page 82 ...

    You can use a SOPC design without using the NIOS processor, you will need to provide your own Avalon MM (memory master) to control the system though. E.g. see this threadhttp://www.alteraforum.com/forum/showthread.php?t=26904 (http://www.alteraforum.com/forum/showthread.php?t=26904)

    Alternatively you can start a non-SOPC project and include a MegaWizard generated SDRAM component. BUT here we are without luck as in QII 10.1SP1 I don't see any support for standard (= non-DDR) SDRAM for Cycone IV (nor for III or II ...). So you will have to 'extract' the one used in the DE0-kit, I suppose.