ALTMEMPHY Debug GUI: Fails Read Resynch Phase Cal Rst

It turns out that the calibration block is only needed if calibrated termination is used in the design. The HPCII MegaWizard by default created a tcl script that set the DDR2 I/O signals to 'calibrated serial 50 ohm'. After changing them to 'serial 50 ohm' (non-calibrated) the design started working. I'm now running the test bench at 150 MHz with signaltap II and the Debug GUI and everything works okay.

I will next bring up the DDR2 clock speed to see how far I can go with uncalibrated serial termination.

question: What is the difference between CALIBRATED and non-calibrated termination? Is it merely the value of the termination resistor that is tuned automatically for ideal signal integrity over PVT? My DDR2 interface is rather slow (150 MHz to 200 MHz will do) so I could likely "get away" with non-calibrated termination (although the RUP/RDN resistors are easy to add in for the next board respin - just in case).