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Altera_Forum
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14 years ago

ALTMEMPHY Debug GUI: Fails Read Resynch Phase Cal Rst

I'm debugging a DDR2 SO-DIMM design that doesn't work (the example top design seemingly doesn't do anything). I enabled the debug interface per the EMI handbook (debug section) and ran the Debug GUI....
Altera_Forum's avatar
Altera_Forum
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14 years ago

I don't have any RUP/RDN pins connected to my FPGA. Apparently, this is needed for the DDR2 interface to function properly? Is there any workaround to salvage the board or will I have to respin the board?