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14 years ago

ALTMEMPHY Debug GUI: Fails Read Resynch Phase Cal Rst

I'm debugging a DDR2 SO-DIMM design that doesn't work (the example top design seemingly doesn't do anything). I enabled the debug interface per the EMI handbook (debug section) and ran the Debug GUI....
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Altera_Forum
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14 years ago

I have also attached the signaltap data file of all signals in my HPCII controller instance. The trace triggered on the first signal (ctl_init_fail). Can anyone spot where the error lies?

So far, by tracing back in the order the signals are asserted right before the trigger, this leads up to the error (older assertions listed first):

HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_seq_wrapper:seq_wrapper|HPC1_phy_alt_mem_phy_seq:seq_inst|HPC1_phy_alt_mem_phy_ctrl:ctrl|mtp_err

HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_seq_wrapper:seq_wrapper|HPC1_phy_alt_mem_phy_seq:seq_inst|HPC1_phy_alt_mem_phy_ctrl:ctrl|ctrl_mmi.ctrl_current_stage.cmd_rrp_reset

HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_seq_wrapper:seq_wrapper|HPC1_phy_alt_mem_phy_seq:seq_inst|HPC1_phy_alt_mem_phy_ctrl:ctrl|dis_state

HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_seq_wrapper:seq_wrapper|HPC1_phy_alt_mem_phy_seq:seq_inst|HPC1_phy_alt_mem_phy_ctrl:ctrl|last_state.s_non_operational

(HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_seq_wrapper:seq_wrapper|HPC1_phy_alt_mem_phy_seq:seq_inst|HPC1_phy_alt_mem_phy_ctrl:ctrl|ctrl_mmi.ctrl_err_code = 17h)

HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_seq_wrapper:seq_wrapper|HPC1_phy_alt_mem_phy_seq:seq_inst|HPC1_phy_alt_mem_phy_ctrl:ctrl|ctrl_mmi.ctrl_calibration_fail

HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_seq_wrapper:seq_wrapper|HPC1_phy_alt_mem_phy_seq:seq_inst|HPC1_phy_alt_mem_phy_ctrl:ctrl|ctrl_mmi.master_state_r.s_non_operational

HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|ctl_cal_fail

It looks like the source seems to be 'mtp_err' which would mean that the problem lies in the PREVIOUS calibration state (MTP Pattern Writes) although reported as successful in the Debug GUI (see earlier posts).

Thanks.