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CFDia's avatar
CFDia
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6 years ago
Solved

ALTLVDS_TX is not able to handle clock tree and assignments during fitting synthesis.

Hello Folks, I have a Quartus custom (no-OS) project for a Stratix IV board which works with an AD9361 daugther board. The project synthesize perfectly and I able to use AD9631 as it should be. Now...
  • CFDia's avatar
    CFDia
    6 years ago

    Hi,

    I have finally found a way around. I just gave up using LVDS for Stratix V. Instead, I used CMOS and ended up rewriting the HDL. It is now working like a charm, but I still need to fix some minor issues.

    With respect to the LVDS, the problem were actually the pins in different banks. It is not possible to "link together" the same clock tree for different banks.

    Thanks for everybody feedback!

    Best Regards.

CFDia's avatar
CFDia
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

I have finally found a way around. I just gave up using LVDS for Stratix V. Instead, I used CMOS and ended up rewriting the HDL. It is now working like a charm, but I still need to fix some minor issues.

With respect to the LVDS, the problem were actually the pins in different banks. It is not possible to "link together" the same clock tree for different banks.

Thanks for everybody feedback!

Best Regards.

Chris2000's avatar
Chris2000
Icon for New Contributor rankNew Contributor
5 years ago

I have the same issue in my design. What speed were you able to get with the CMOS interface?