Forum Discussion
New ContributorALTLVDS_TX is not able to handle clock tree and assignments during fitting synthesis.
Hi,
I have finally found a way around. I just gave up using LVDS for Stratix V. Instead, I used CMOS and ended up rewriting the HDL. It is now working like a charm, but I still need to fix some minor issues.
With respect to the LVDS, the problem were actually the pins in different banks. It is not possible to "link together" the same clock tree for different banks.
Thanks for everybody feedback!
Best Regards.
New ContributorHi,
I have finally found a way around. I just gave up using LVDS for Stratix V. Instead, I used CMOS and ended up rewriting the HDL. It is now working like a charm, but I still need to fix some minor issues.
With respect to the LVDS, the problem were actually the pins in different banks. It is not possible to "link together" the same clock tree for different banks.
Thanks for everybody feedback!
Best Regards.
Chris2000I have the same issue in my design. What speed were you able to get with the CMOS interface?
