Forum Discussion
New ContributorALTLVDS_TX is not able to handle clock tree and assignments during fitting synthesis.
Hi,
I have finally found a way around. I just gave up using LVDS for Stratix V. Instead, I used CMOS and ended up rewriting the HDL. It is now working like a charm, but I still need to fix some minor issues.
With respect to the LVDS, the problem were actually the pins in different banks. It is not possible to "link together" the same clock tree for different banks.
Thanks for everybody feedback!
Best Regards.
Frequent ContributorHi ,
I have gone in depth to your code, the issue is with the pin assignment with the TX pins.
The issue is with the pin assignment on the LVDS Tx IP
The IO pin placement given for the LVDS Tx IP is 7B and 4B, so the clock cannot constrain ( route to both banks). That makes the fitter to fail.
Attached the screen shot of the problematic pin placement in the screen shot and also the successful compiled the project after removing the LVDS TX pin placement.
New ContributorIt seems the fitting works when different banks are used. I checked the Stratix IV (which the complete synthesis is success) and the pin assigment has pins in different banks for same TX bus using LVDS. Please, check the screenshot. It uses 5C and 5A banks. Why in this case there is no clock tree complaining?
- Rahul_S_Intel1
To be precise the Stratix V and And Stratix IV are having different architecture that is the reason
And to answer the above thread questions, I have a suggestion to try different LVDS IP for each bank and the clock source.
- CFDia
That seems a very good idea. Do you mean create a new instance just for the problematic pins? I'll try this and get back with the result...
