Forum Discussion
New ContributorALTLVDS_TX is not able to handle clock tree and assignments during fitting synthesis.
Hi,
I have finally found a way around. I just gave up using LVDS for Stratix V. Instead, I used CMOS and ended up rewriting the HDL. It is now working like a charm, but I still need to fix some minor issues.
With respect to the LVDS, the problem were actually the pins in different banks. It is not possible to "link together" the same clock tree for different banks.
Thanks for everybody feedback!
Best Regards.
Frequent ContributorHi ,
I have gone in depth to your code, the issue is with the pin assignment with the TX pins.
The issue is with the pin assignment on the LVDS Tx IP
The IO pin placement given for the LVDS Tx IP is 7B and 4B, so the clock cannot constrain ( route to both banks). That makes the fitter to fail.
Attached the screen shot of the problematic pin placement in the screen shot and also the successful compiled the project after removing the LVDS TX pin placement.
New ContributorHello!
Thanks for your help! Some time ago, I ended up concluding the fit would work after removing the problematic TX pins. Unfortunately, I need these pins to make my application work. The pins are required to interface with the following daughter board:
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=65&No=946&PartNo=4
So, the TX pins has specific assignments. If I cannot assign the deleted pins then the daughter board is incompatible with Stratix V. Is that true? Is is possible to find a way around and make clock routes for both 7B and 4B banks?
