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CFDia's avatar
CFDia
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7 years ago
Solved

ALTLVDS_TX is not able to handle clock tree and assignments during fitting synthesis.

Hello Folks, I have a Quartus custom (no-OS) project for a Stratix IV board which works with an AD9361 daugther board. The project synthesize perfectly and I able to use AD9631 as it should be. Now...
  • CFDia's avatar
    CFDia
    6 years ago

    Hi,

    I have finally found a way around. I just gave up using LVDS for Stratix V. Instead, I used CMOS and ended up rewriting the HDL. It is now working like a charm, but I still need to fix some minor issues.

    With respect to the LVDS, the problem were actually the pins in different banks. It is not possible to "link together" the same clock tree for different banks.

    Thanks for everybody feedback!

    Best Regards.

Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi ,

Check the IO pins and clock is compact to the Stratix V IO user guidelines. And also check by mistake using the transceiver pins. If using the transceiver pins , the above error will occur

  • CFDia's avatar
    CFDia
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hello RSree,

    Thanks for your reply. What do you mean with compact to the Stratix V? Would you mind tell me what is it?

    I checked assigment table from Stratix V development board. What else should I check beyond pin assigment and LVDS. I am quite sure that they are correctly assigned.

    Is there anything on Megafunction properties that I should change?

    • Rahul_S_Intel1's avatar
      Rahul_S_Intel1
      Icon for Frequent Contributor rankFrequent Contributor
      7 years ago

      Hi,

      The Pin assignment I mean,is that correct is it correctly assigned .By mistake it is not assigned to any transceiver pins.

      If possible can you please send a sample project which makes the error so that I can comment what is the exact issue.

      Re

    • CFDia's avatar
      CFDia
      Icon for New Contributor rankNew Contributor
      7 years ago

      Hi,

      Here is a sample of the project which results in error. Please, let me know what are your impressions.

      Thanks!

    • Rahul_S_Intel1's avatar
      Rahul_S_Intel1
      Icon for Frequent Contributor rankFrequent Contributor
      7 years ago

      Hi ,

      I have done the below for the isolation of the issue.

      1. Compiled the project in 19.1 Quartus got the fitter Error.
      2. Made the pin assignment to auto project got successfully compiled. This means to say that the logic is fine

      Next action.

      Try to isolate the error which pins are making the error.

      Initial the hsma_d signal is giving the error, when I try to isolate, another fitter is occurring, So I need time to understand the code and how you have initialized the code to LVDS and PLL ip. Here I feel there should have done some violation.

      Let me go through it and I will update you.