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Altera_Forum
Honored Contributor
Honored ContributorALTLVDS_RX Old & New
Can anyone tell my why ALTLVDS_RX with an external PLL requires; 1 clock at data_rate/2 when using Quartus 13.1 1 clock at data_rate + 1 clock at data_rate/deser-factor when using Quartus ...
Altera_ForumHonored Contributor
Honored ContributorNo problem. Paying it forward, as I've certainly wasted a lot of Altera engineering's time looking into mistakes on my part. : )
