Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorALTLVDS_RX Old & New
Can anyone tell my why ALTLVDS_RX with an external PLL requires; 1 clock at data_rate/2 when using Quartus 13.1 1 clock at data_rate + 1 clock at data_rate/deser-factor when using Quartus ...
Altera_ForumHonored Contributor
Honored ContributorYou are correct, and I offer my sincerest apologies if I wasted your time. I didn't realize the Q13.1 design was targeting the Cyclone IV, as you correctly deduced.
